A Near Memory Computing FPGA Architecture for Neural Network Acceleration

The Deep Learning Accelerators (DLAs) are gaining attention in recent years due to their advantages in effi-ciency, privacy, and bandwidth usage efficiency to operate deep neural networks. Field Programmable Gate Arrays (FPGAs) can offer low-power computation capacity, which is profound for the deployment of DLAs in AI edge computing devices. However, there are two major problems in deploying DLAsin FPGA: Firstly, processor and memory units in FPGA are separated, and the data transfer between them requires a large energy overhead. Secondly, the complexity of Deep Neural Network (DNN) models and the variety of FPGA platforms make it hard to design hardware accelerators when taking into account both performance and energy efficiency simultaneously. Near-Memory-Computing (NMC) has been a promising candidate to accelerate neural network computing. Therefore, this paper proposes an NMC FPGA architecture, which can be adapted to various neural network models by using Verilog-to-Routing (VTR) tool.