A Latency-resource Aware FPGA Implementation of TCAM-based FIB

The development of networking devices aims at better Quality of Service (QoS) of modern networks. Forwarding information base (FIB) has been designed and optimized for faster packet forwarding over the past few decades. This paper proposes a low-latency and resource-saving TCAM-based FIB design. The distributed LUTRAM resource on FPGA is utilized and optimized to implement the TCAM module. In a
$512\times 36$
single-cycle FIB experiment on Xilinx Vertex-7, the proposed design achieves 6.2 ns in lookup latency with 0 BRAM and 1508 SLICEs (5094 LUTs). Furthermore, the lookup latency, the LUT resource consumption, and the power consumption increase approximately linearly with the growth of FIB size, FIB width, and the number of output interfaces, respectively. The proposed FIB design has good scalability on the FPGA platform and may be useful for the development of large-scale ad hoc networks.