A Ka-Band Frequency Doubler With a Broadband Matching Scheme for Efficiency Optimization

Caused by inappropriate allocation of the interstage power mismatches during broadband matching, the boosted dynamic dc current of the frequency doubler (FD) would deteriorate the broadband efficiency. To tackle this issue, an efficiency-optimized broadband matching strategy is proposed by allocating all of the desired low-frequency mismatches ahead of the push-push (PP) pair, which not only keeps a broadband output but also reduces the dynamic dc current and improves the efficiency over the entire operating bandwidth simultaneously. To further enhance the 2nd harmonic (HR2) output power, a fourth-order notch filter is also designed at the PP pair input. Fabricated in a 65-nm CMOS process, the proposed Ka-band FD exhibits >15% efficiency from 24.6 to 36 GHz, and a 23.5% peak efficiency is achieved. A 42.6% fractional bandwidth (FBW) is also realized with a fundamental rejection ratio (FRR) over 45 dBc.