Low Insertion Loss CMOS Phase Shifter for Wireless Power Transfer System

In this study, we propose an optimization method for achieving low insertion loss (IL) and small size of phase shifter. To reduce the large size of the switch type phase shifter (STPS), an asymmetric high-pass (HP)/low-pass (LP) topology configuration was employed, where the 180° bit was subjected to a 110° shift and a 70° delay. In order to minimize the IL of the 180° phase shifter, transistors with sufficiently large widths were used in the HP/LP structure, even if they had low isolation. The size of the proposed phase shifter was
$0.53\times0.25$
mm
$^{\mathbf {2}}$
(
$0.044\lambda \times 0.021\lambda $
). The 6-bit PS has a low IL of
$ < 7.4$
dB, low root mean square (rms) phase error of
$ < 3^{\circ }$
, low rms amplitude error of
$ < 0.48$
dB, and 1-dB power compression point
$>5.0$
dBm in 23.4–25.6 GHz.