A High-Linearity 7–9-GHz Receiver Front End With Strength-Oriented Nonlinearity Cancellation

This letter presents a 7–9-GHz four-element eight-beam receiver front end (FE) in 65-nm CMOS for satellite communications. To boost the linearity and defeat interferences, the FE proposes a strength-oriented nonlinearity cancellation (SoNC) technique based on multigate transistors (MGTRs). It demonstrates a 22-dB single-element gain with a 7-dB noise figure (NF) at 7.5 GHz. The measured input-referred 1-dB gain compression point (IP
$_{\mathrm {1\, dB}}$
) and third-order input interception point (IIP
₃
) at 7.5 GHz are −12 and −7.5 dBm, respectively. The chip occupies 19.8 mm
²
and consumes 1265 mW, and achieves an excellent linearity among silicon-based RF-beamforming receivers.