Design and Analysis of a Dual Clock Edge-Triggered Divide-by-Four Divider

A simple structure is proposed for a divide-by-four frequency divider implemented in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-
$\mu \text{m}$
CMOS process. The proposed divider based on a dual clock edge-trigged topology and a simple structure can handle higher frequencies with lower current dissipation and fewer transistor counts than those with a traditional divide-by-four structure. With a power supply of 1.8 V, the proposed divider dissipated a 2.55-mA current and achieved a 16.9% frequency tuning range ranging from 4.96 to 5.88 GHz. The chip size of the proposed divider core only occupies
$144\times133\,\,\mu \text{m}^{2}$
.