In-Memory Multi-Bit Multiplication and Accumulation (MAC) Using FeFET for Energy Efficient IoT

To meet the huge computing demands of data-intensive applications, resource constrained IoT devices have to address the data migration issue, i.e., memory wall, in the conventional Von Neumann architecture to achieve the desired energy efficiency. Recently, Computing-in-Memory (CiM) has been considered as a promising alternative to overcome memory wall and extensively investigated for its deployment in IoT devices using SRAM, DRAM and Non-Volatile Memory (NVM). Among various devices, FeFET (Ferroelectric FET) is an non-volatile device option featured with separate write/read paths and large on/off ratio, etc, thus is promising for building CiM designs. In this paper, we propose a multi-bit CiM design using 2-FeFET memory that can directly perform the key multiplication and accumulation (MAC) operation of neural networks as well as more complex convolution and matrix-vector multiplication. In addition, we investigate the impact of the device non-linearity on the MAC output, and propose to use a non-linear quantization and mapping between the discharge time and the FeFET polarization state to further improve the operation linearity. Experiment results show that the proposed design can achieve desirable accuracy, with almost $6\times$ fewer transistors than 6T SRAM array, when implementing the same computation, as well as $1.42\times$ improvement in energy efficiency.