Analysis of High-temperature Parasitic False Turn-on in a SiC MOSFET Half-bridge Circuit

Circuit-level analysis for parasitic false turn-on for SiC MOSFET half-bridge configuration in high temperature environment is described in this paper. At turn-on transient in a half-bridge circuit, the companion MOSFET might suffer the false turn-on when the induced positive gate-source voltage is higher than the threshold voltage $(V_{th)}$. According to analysis with KCL theorem. The false-on risk of the companion MOSFET will increase with increasing the turn-off resistance of the companion MOSFET. It is found that the false-on risk will decrease at $175^{\circ} C$ environment compared with at room temperature. Hence, this paper builds the analytical model to explains this phenomenon. In high-temperature environment, the V
th
will decrease, but the induced gate-source voltage will reduce due to the weaker Miller effect. The analytical model is proposed to validate this false turn-on phenomenon at high temperature. TO247-packaged SiC MOSFET is used in the experimental results.