Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows

Process variation has proven to be one of the higher impacting factors in modern Application-Specific Integrated Circuit (ASIC) flows Quality of Results (QoR). On the one hand, the excessive MOSFET shrinking, in combination with the less potent metallization layers shrinking ability at cutting edge technology nodes, has rendered process variation effects more and more pronounced. On the other hand, the ever-increasing market competition between hi-tech semiconductor companies has promoted the adoption of immature, emerging technology nodes, which are not adequately calibrated for high yield in mass production. To cope with these issues, the industry has adopted a test-calibrate-produce strategy, meaning that design-specific golden silicon data are obtained by relatively inexpensive test chip fabrication runs and then are used to calibrate the ASIC flow for highest possible yield on expensive mass production, accordingly. These golden data are typically used at the ASIC flow Back-End, i. e. Place & Route, Clock Tree Synthesis, In-Place Optimization, Sign-Off. In this work, we present a deterministic and a Monte-Carlo based methodology, capable of providing an insight of inter-wafer and intra-die process variation impact, at the post-synthesis gate level, to provide a better initial solution to the ASIC Back-End. Both methodologies were tested using four open-source designs for 4 different technology libraries at 250, 130, 40, and 7 nm, and yield 9.74% improvement in total cell area and 22.14% improvement in leakage power, on average, over netlists synthesized at worst case, while meeting worst-case timing for all libraries. Also, our Monte-Carlo methodology provides a predictive view on the random variation impact on netlists synthesized at typical corner.