Efficient Dynamic Logic Magnitude Comparators

Digital magnitude comparators are used in digital systems to compare two binary numbers and to determine if the numbers are equal, or if one number is greater or less than the other. In this work the design of magnitude comparators in dynamic logic is examined. Two dynamic logic magnitude comparator designs are proposed and compared. One of these designs exploits an existing simplification, while the other is a totally new one. The new dynamic logic comparator design compared over the one based on the existing simplification, shows less hardware complexity, consumes less power and has lower power delay-product, for typical operand widths.