Impact of Sheet Width and Silicon Height in 3D Stacked Nanosheet GAA Transistor Technology

Silicon height, width, and number of 3D stacked nanosheet layers are optimized in this paper to achieve lower power consumption, enhanced integration density, and higher performance with gate all-around (GAA) 3D stacked nanosheet transistors. Electrical characteristics of vertically stacked nanosheet transistors are compared with FinFETs under equal silicon area and ON current constraints. Assuming a tight vertical silicon sheet pitch of 5nm, test circuits with the vertically stacked nanowires provide comparable speed with active mode energy consumption, silicon area, and idle mode leakage power consumption savings of up to 40.24%, 21.81%, and 63.58%, respectively, as compared to FinFETs in a 5nm CMOS technology.