16 Gbps, 19.6mW Ultralow-Power-Consumption Continuous-phase Frequency-shift-keying Transmitter in 65 nm CMOS technology

This paper presents an ultralow power-consumption, high data-rate continuous-phase frequency-shift-keying (CPFSK) transmitter (TX). The TX mainly consists of a high-speed digitally controlled oscillator (DCO), a pseudorandom bit sequence (PRBS) generator, a wideband input clock butter and a CML-to-CMOS converter. The DCO is used to generate two carrier frequencies of $\approx 70 {\mathrm{GHz}}$ and $\approx 75 {\mathrm{GHz}}$. In order to achieve a low power consumption, high quality (Q) - factor inductors and capacitors are deliberately implemented in the DCO, and a high-speed switch is designed to obtain a high data rate. A half-rate, fully-differential PRBS generator with asynchronous XOR is also integrated for testing purposes. The TX was implemented in TSMC 65 nm CMOS with a chip size of $0.8 {\mathrm{mm}} \times 0.6 {\mathrm{mm}}$. The highest data rate of 16 Gbps is measured in the frequency domain. The DC power consumption of 19.6 mW from a 1.2V supply voltage is measured without the PRBS generator leading to an energy efficiency per bit of 1.225 pJ/bit. Due to its low power consumption and high data rate, the proposed TX is suitable for indoor short-range wireless communication and could also be adapted for future 6G mobile communication.