I. Introduction
Multibit/cycle successive approximation register (SAR) analog-to-digital converters (ADCs) combine the benefits of the flash ADC and single bit/cycle SAR ADC, and thus are favored in the applications that require 6-10bit 0.1-2GS/s ADCs [1] –[7]. However, since a multibit quantizer is needed in each comparison cycle in a multibit/cycle SAR ADC, the ADC performance is limited by the resolution of the quantizer. Moreover, a reference generator is needed to provide multiple reference voltages for the quantizer, which draws nonnegligible power consumption. In addition, the speed of the ADC is limited by the multibit operation due to the extra digital logics.