Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees

Process variations have emerged as a severe performance bottleneck for advanced technology nodes. This paper investigates the delay behavior of a range of exact and incomplete parallel-prefix addition trees under variations, including speculative/approximate trees and trees with duplicated prefix nodes. The performance of a range of incomplete adder variants is investigated comparatively with conventional exact architectures at a 16-nm technology node. In order to capture variations generated from a range of process-dependent sources and their impact on delay characteristics, the analysis considers threshold voltage variations employing Spice-level simulations. Under nominal voltage and in the presence of threshold variations, incomplete architectures are found to still offer a smaller worst-case delay than their exact counterparts; similarly for a low-voltage scenario, where the supply voltage is reduced to 0.8 V. However, focusing on normalized delay variation, it is here found that incomplete-tree adders are more susceptible to variations as they show a wider delay spread than exact architectures around their respective mean values. As a remedy, it is shown that the number of stages in an incomplete adder can be used as a design parameter to investigate accuracy vs. variability-tolerance trade-offs. Furthermore, by duplicating delay-critical paths of prefix trees, worst-case delay and standard deviation reduce compared to the exact architectures.