A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time

This paper proposes a novel hybrid-triggered electrostatic discharge (ESD) power clamp circuit. By co- optimizing the transient and static triggered paths, the proposed circuit can achieve transient response time over 6 times longer than that of traditional transient circuit in the same footprint, thus greatly improving area efficiency. The trigger circuit (TC) area of the proposed circuit reduces 50% compared to the baseline circuit. In addition, the circuit achieves high false- trigger immunity and low leakage current of 7 nA. The proposed circuit achieves adjustable transient response time to accommodate different ESD events with high flexibility. All the studied circuits are fabricated using a 28-nm CMOS process. To verify the proposed circuit, the simulation and test results are analyzed in detail for this paper.