A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise

This paper presents a novel fully synthesizable dynamic latched comparator with reduced kickback noise. A dynamic latched comparator is attractive to low power and high speed applications, but suffers from kickback noise. Although several kickback noise reduction techniques have been widely used, none of them can apply to synthesizable design flow. Inspired by the isolation technique, this paper employs OAI22 (4-input OR-AND-INVERT) gates to replace the NAND3 (3-input NAND) gates in the input stage of the conventional synthesizable dynamic latched comparator, so that the kickback noise can be significantly reduced due to the inherent isolation transistor in OAI22. Simulated in 28nm process, the proposed OAI22-based comparator achieves the maximum kickback noise of 8.63mV, compared with that of 46.16mV in the NAND3-based counterpart.