A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM

We present a hybrid phase-detection based switching controller incorporating a look-up table (LUT) based finite state machine (FSM). This FSM can help in improving the settling response in fractional-N digital phase-locked loops (DPLLs). The settling time of the DPLL is further improved by using a grey counter-based coarse time-to-digital converter (TDC), which avoids metastability issues arising in binary counter-based TDC. A 2.7-5.5 GHz gear-shift mechanism based ring-oscillator fractional-N DPLL (FNDPLL) has been implemented in the CMOS 65-nm LL technology. The MATLAB and cadence simulation results of the FNDPLL show that the system with the reference clock ($F_{r\mathrm{e}f}$) of 100MHz can achieve a worst-case settling time of 3$\mu$s over an octave tuning range with 28 mW of power consumption.