Optimal Distribution of High-Speed Clocks on Transceiver Chips

A methodology is proposed for the optimum design of on-chip transmission lines carrying high-speed clocks. Differential metal 9 or stacked metal 8/metal 9 geometries with no ground plane emerge as best choices. Moreover, CMOS and CML signaling schemes are compared for clock distribution. It is shown that CMOS clocks are better suited for frequencies up to 20 GHz and line lengths up to 5 mm.