Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process

This investigation presents a low-power 1-kb SRAM, where memory cells are based on skewed inverter design. More specifically, Schmitt trigger inverters are utilized in the cell to enhance read, write, and hold capabilities. To minimize power usage, a supply voltage selection circuit is included to the proposed cell, where the supply voltage of the cells is selected in different nodes. The 1-kb SRAM is designed using a typical 40-nm CMOS. The post-layout simulation is presented to verify the low power consumption. The design is operated at 100 MHz clock with an energy per bit simulated to be 5.968 fJ given VDD=0.8 V. The energy/access is simulated to be 0.191 pJ in the same condition.