Exploring the stacking of devices in a vertical nanowire to implement IC

Stacking devices in a 3D configuration by using a vertical topology are the next step to reduce electronic devices and circuits area foot-print. We propose the realization of a CMOS inverter by multiple sequential deposition of inter-metal and metal layers around a vertical NW. This new device concept is simulated and optimized by using Sentaurus 3D TCAD simulations. We prove the suitability of this proposal and analyze the influence of different device design parameters to enhance its performance.