Design of a 5G Application CML Frequency Divider for Improved Efficiency

An injection locked frequency divide-by-two current mode logic (CML) with injection directly through the bias tail current is implemented with reduced circuitry complexity and reduced power consumption. The proposed topology is capable of operating with a lower voltage supply compared to a conventional CML frequency divider topology with a maintained output voltage swing. A design guide for a given self-resonance frequency suitable for first cut design is proposed to estimate the optimal power consumption. A proof-of-concept of the proposed topology together with a conventional CML divider are implemented in an in-house BiCMOS process. The proposed topology occupies a silicon area of 0.0014 mm
²
, and on-chip measurements show a locking range of 41.5 GHz, from 2 GHz to 43.5 GHz. The DC power consumption is 3.55 mW.