I. Introduction
As the nanotech gets smaller and reduces in size, it is aiding the fruition of better and more robust smart devices (along with faster communication links) to sprout in the digital domain and electronics atmosphere. Unfortunately with the good also comes a slew of new challenges for designers and engineers; especially as the technology shifts from an analog paradigm to a digital one due to confinements and restrictions of the physically quantized fabrication limits (such as transistor gate width restraints). At the heart of most of these smart devices is some sort of ticking clock with a tracker: such as a phase-locked loop (PLL), delay locked loop (DLL), or an injection locked synchronizer; and the actual timing ticker is generated by some sort of oscillator (whether ring, LC or otherwise). LC tanked oscillators (especially the negative gm (-gm) pair variety) tend to be excellent for low phase noise (PN) generation. And as the trend moves towards a digital world, so too is this type of oscillator.