Design of a Novel Encoder for Flash Analog to Digital Converter

Analog to digital converters (ADC) are extensively used as a basic component in signal processing systems to convert the available analog signals to digital signals. Flash ADC, also called as parallel ADC offer high speed conversion than other ADCs. The major issues occurring in the Flash ADC are the response time of comparators and speed of thermometer to binary encoder. Therefore, different designs have been proposed previously for both comparators and encoders to overcome these issues. This work is centred on the encoder and reviews the different designs of encoders such as multiplexers, adders, adders with majority gates as its carry function and XOR-MAJ encoder. A novel encoder is proposed which is designed using full adders to reduce the number of transistors and eventually reducing number of capacitance nodes to reduce delay. The design is simulated at 130nm CMOS technology using Mentor Graphics EDA tool. The comparison of designs shows the worst-case delay, number of transistors and power consumption. The result analysis show that the novel encoder uses 92 transistors with the worst-case delay of 144.77 ns but the power dissipation is about 51.34 nW which is comparatively highest. Hence the analysis shows the novel encoder can be used when the constraints are number of transistors and delay but not for low power applications.