An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier

An auxiliary receiver is proposed, including a high dynamic range low-noise amplifier and second-order baseband filter to improve the compression point with low power dissipation. The receiver has high input impedance and it can be placed at the transmitter output without loading effects. Implemented in a 28nm CMOS technology it occupies an active area of 0.5 mm
²
. The receiver has a measured NF of 6 dB and it can withstand up to +7 dBm continuous waveform (CW) signal at 80 MHz offset with less than 1-dB gain compression. The signal path and the clock generation circuits consume 27 mW and 20 mW at 2 GHz respectively.