A 111-149-GHz, Compact Power-combined Amplifier With 17.5-dBm $P_{sat}$, 16.5% PAE in 22-nm CMOS FD-SOI

This paper presents a 4-way, 3-stage power-combined CMOS SOI power amplifier (PA) operating from 111–149 GHz. Pseudo-differential stages and 4-way parallel power combining increases the output power from power cells matched to 50 Ohms. Using sub-quarter wavelength (SQWL)-type coupled-line balun (CLB), low-loss output matching networks achieve higher power-added efficiency (PAE). Fabricated in 22-nm FD-SOI CMOS technology, the PA occupies 0.113mm2 core area generates 17.5-dBm saturated output power (P
sat
) and 16.5% peak PAE. To the author's knowledge, this work demonstrates the highest PAE in a CMOS SOI process at D-band.