Integrated NMOS Differential Amplifier

A single-channel integrated differential amplifier has been designed using Negative-channel Metal-Oxide-Semiconductor (NMOS) technology. The main interest is to establish the correct operating point. Following the integrated circuit design flow a schematic circuit is proposed, this is designed from an active voltage divider copies whose reference voltages are 0.25V
DD
and 0.5V
DD
whereas V
DD
= 5 V. The circuit simulation has been realized in Virtuoso considering the level 3 SPICE model, and results show that for proposed dc levels (2.5 V and 1.25 V) the devices work in the saturation region, obtaining a low-frequency gain of 18 dB. Finally, a physical design is realized in Electric VLSI considering specific experiments oriented to Design For Test (DFT) in order to perform the integrated circuit testing using on-wafer measurement equipment.