Acceleration of Radio Direction Finder Algorithm in FPGA Computing Platform

This work is focused on Digital Signal Processing (DSP) implementation of a radio direction finder demonstrator and acceleration of its most computing-intensive operations in a Field Programmable Gate Array (FPGA). The hardware layer of the demonstrator consists of an Software Defined Radio (SDR) device and receiving array arranged from four unidirectional antennas. The implemented solution uses Fast Fourier Transform (FFT) calculated in the FPGA synchronously for the four receiving channels. The calculation results show an approximately linear relationship between the algorithm’s response and the actual azimuth of the incoming radio wave. Simulations in the Matlab computing environment verified the algorithm’s operation in a simplified scenario. The radio direction finder module was integrated with the FPGA device as part of the National Instruments (NI) USRP 2955 radio receiver. Practical experiments were then conducted using a portable Private Mobile Radio (PMR) transceiver as a signal source. The experimental results showed a substantial improvement in the processing speed achieved by moving the computations from the host’s processor to the FPGA.