Parametric Study of The Geometry Design of Through-silicon Via in Silicon Interposer

Silicon interposer has been widely used in advanced IC packages as the interconnection to achieve heterogeneous integration and higher packaging density. However, thermomechanical reliability concerns of silicon interposers induced by the CTE mismatch between the silicon and the through-silicon vias (copper) need to be well understood. This study investigates the reliability of silicon interposers with different combinations of design parameters including the diameter and the pitch of the vias, and the thickness of the silicon substrate during the thermal cycling. The temperature profile is from room temperature (RT) 23°C to 400°C and then cooled to RT. Based on the numerical simulation, the protrusion of the copper via and the in-plane deformation of the silicon during thermal cycling are obtained. Unrecoverable copper protrusions are observed because of the creep behavior of the copper at high temperatures. The max. principal stress of the silicon substrate during thermal cycling is utilized to assess the reliability of the silicon for potential cracking failure. Furthermore, a machine learning model based on an artificial neural network (ANN) is developed, which reduces the computational time from 1.5 hours to 10 seconds. This well-trained ANN model can be used in the design stage of the silicon interposer to obtain the optimum design parameters.