Chip-level Thermal Simulation for a Multicore Processor Using a Multi-Block Model Enabled by Proper Orthogonal Decomposition

To perform chip-level thermal simulation effectively for large-scale processors with multicores/manycores, a multi-block model enabled by proper orthogonal decomposition (POD) and domain decomposition is applied. This approach partitions a large-scale processor into smaller building blocks, such as cores, caches, I/O units, etc. For each building block, a set of temperature solution data accounting for parametric variations of interest is collected individually from FEniCS, a finite element simulation platform, to extract its basis functions (or POD modes). Using smaller building blocks, the multi-block approach significantly enhances the computational efficiency of POD mode generation to construct a POD model for the entire chip. In this work, a set of POD modes is trained by the solution data from each of two selected building blocks, a core and a level-2 cache, of AMD Athlon II X4 610e, a quad-core chip. A two-block POD thermal model is developed for Core 1 and L2 Cache by projecting these two blocks to a functional space represented by these 2 sets of POD modes. The discontinuous Galerkin method with the penalty number is applied to ensure the boundary continuity at the block interface. An optimal range of the penalty number for the two-block POD thermal model has been observed to provide an accurate prediction of the dynamic thermal distribution in Core 1 and L2 Cache. For the two-block POD model, a least square error below 3% is achieved with only 3 POD modes in each block. This results in a reduction in the numerical degrees of freedom by almost 4 orders in magnitude and thousands of times faster than FEniCS for the thermal simulation.