A Built-in Spice Time-domain Variation Model of the BTI-induced Random Trap Fluctuation (RTF) in 14 nm FinFETs

In the advanced FinFET technology, variability has been one of the main scaling concerns. The undesirable variation sources will be finally reflected in real circuit operation. In this paper, a carrier transport mechanism based on Virtual Source Model was first developed. Then, the BTI-induced degradation of device performance after long time operation is discussed. The technique of Random Trap Profiling is used to profile the lateral trap density in the channel from the source to drain. Then, a variation model from the level of device to circuit was built by Virtual Source Model. Finally, the model was implemented in Spice which can simulate the behavior of basic logic gate.