SEVA: Structural Analysis based Security Evaluation of Sequential Locking

The protection of hardware intellectual properties (IPs) against reverse engineering and piracy has emerged as a critical need over the past decade. These threats are expected to remain dominant due to the following reasons: (1) prevalence of IP-based System on Chip (SoC) design flow; (2) highly globalized supply chain of hardware IP blocks; and (3) the presence of multiple untrusted parties in the SoC life cycle. Consequently, design solutions to safeguard hardware IPs against these threats have become a topic of active research. Hardware obfuscation or locking techniques have shown tremendous promise to provide robust low-cost protection against these threats. However, while researchers have explored innovative locking-based protections, a vast body of research on effective attacks on these techniques exposing their vulnerabilities has been presented. The latter forms an important and valuable contribution to the field of hardware security since it helps to understand potential vulnerabilities of locking solutions; perform security evaluation, and mitigate known vulnerabilities to entail more robust protection. In this paper, we present SEVA, a novel paradigm of structural analysis attack on sequential locking. SEVA aims at identifying and removing the inserted logic and the sequential elements in a design that is used to transform and lock its state space. We demonstrate that the proposed attack is highly scalable and precise, and widely applicable to many state-of-the-art sequential locking techniques. Based on the available information to an attacker, SEVA offers two attack modes, supervised and unsupervised machine learning (ML) analysis. We have performed the security evaluation to multiple sequential techniques and successfully identified the added state elements (SEs) with an average accuracy of 97%.