I. Introduction
In fan-out packaging (FOP), various forms of wafer level packaging (WLP) and panel level packaging (PLP) have been widely demonstrated, in this paper, we take the regular eWLB process as an example shown in Figure 1. In general, the fabrication nodes of a FOP refer to preparing a carrier with temporary adhesive material, attaching the chips onto the carrier, and then encapsulating the bonded chips with EMC to form a reconstructed piece. The newly formed piece can then be de-bonded from the carrier and go through the routing and ball drop processes. Among them, the EMC and temporary bond material are key to the process. This is also true for other packaging architectures that take the FO form as part of the final packaging products, such as some large-scale SiP or heterogenous integrated products, FO on the substrate, 2.5D or 3D on the organic interposer, and so on.