Power Integrity Solution While Package integrating Multi-Die

As increasingly high demand on system integration and performance, system in package (SIP) has become one of the mainstream packaging forms in a scalable and cost-effective way. However, the number of chips and stacked layers increase, resulting in increasingly prominent power integrity issues. Compared to PCB design, PI optimization strategies for package substrate are limited. In this paper, an innovative substrate design scheme is proposed to optimize the substrate design with the lowest coupled noise based on the frequency domain impedance analysis of the power distribution network, thereby improving the power integrity of the product.