Jitter Addition Methodology for DDR5 Tx IBIS Model

This paper proposes a methodology for including random jitter (Rj), deterministic jitter (Dj) for existing IBIS transmitter (Tx) model using pre-defined models of commercial EDA tools. This paper also addresses the limitation and criteria’s to be met before applying this methodology. By adding Rj, Dj to Tx IBIS model, total jitter (Tj) at specified bit error rate (BER) can be evaluated with reasonable accuracy, thus enabling interfaces like DDR5 to be modelled with jitter effects.