Optimization of Micro-interconnection Distribution of Gold Stud Bumps for Thermo-sonic Flip Chip Bonding

With the scaling down of broadband RF integration circuits, themo-sonic flip chip (TSFC) bonding based on Au stud bump has become an important packaging technique for its simpler and more convenient assembly process, compared with solder bump reflow flip chip bonding and anisotropic conductive film flip chip bonding. However, due to the decreasing chip thickness to meet the requirements of IC package and improve the heat conductive properties, the requirements on TSFC bonding parameters are higher, especially for bonding force, to avoid chip fragmentation and reliability problems. In this paper, a numerical model was proposed to avoid stress concentration during TSFC bonding by optimizing the distribution of pads and gold bumps on the chip, to expand the process window and reduce the risk of debris. Finite element software, COMSOL Multiphysics was used to analyze the relationship between surface stress and gold bump spacing. The gold stud bumps used in the simulation are 70 μm in diameter and 50um in height. The simulation results indicate that the surface stress distribution is affected by both the number and distribution of the bumps. For the same bonding force, the maximum stress for the chip with one bump is larger than that with two bumps. The stress in the center of two bumps reached the minimum value when the spacing is 260um. When the bump spacing is between 260μm and 300μm, both the maximum stress and the maximum stress difference on the chip are maintained at lower levels, and the deformation of the chip is relatively small. During the TSFC bonding, the risk of debris can be reduced to a lower level.