Development of a Method for Reducing the Power, Area and Delay Time for a Static Random Access Memory Cell

This paper proposes a method for reducing the power, area and delay time for a Static Random-Access Memory (SRAM) cell. The critical optimization for SRAM cells is the product of power, area, and delay (PAD). This article represents a hybrid cell assignment method based on multi-sized and dual-Vth SRAM cells which improve the PAD cost function by 29%. The simulation results in a 5nm technology show that combining the used hybrid cell assignment and the cell sizing methods can lower PAD by up to 36% when compared to the conventional cell design and assignment.