Hardware-Efficient Implementation of Piece-wise Digital Predistorters for Wideband 5G Transmitters

This paper proposes a hardware-efficient implementation of the digital predistortion (DPD) engine in wideband fifth-generation (5G) transmitters. This efficient implementation employs a DPD model comprising a piece-wise linear (PWL) function that covers unequal non-overlapping segments of the squared magnitude of the input signal range. When compared with prior works, the proposed PWL-based model is less complex in that it does not require the implementation of the square-root function. Furthermore, a parallelized implementation of the PWL-based DPD engine is proposed to reduce the required hardware processing rate. Compared to previous works, the proposed implementation simplifies the on-chip routing structure needed.