ASIC Implementation of UART chip having 16 Baud Rates at SCL 180 nm Technology Node

This paper presents the design and implementation of the UART module on the ASIC chip using SCL 180 nm technology. The architecture of UART consists of three blocks: Signal Control (SC), Baud Rate Generator (BG), Transmitter (Tx), and Receiver (Rx). It is designed to work in a full- duplex communication mode with sixteen numbers baud rates from 0.4800 kbps to 260.42 kbps at 50 MHz external clock, control, and status check pins are provided to set the baud rate and check the status of the transmitter and receiver. The external dock is first divided by a dividing factor to generate a BCLK clock through a baud rate generator and then divided by sixteen in the transmitter and receiver block. UART blocks are designed by RTL coding applying state machine concept and simulated in Verilog Compiler and Simulator (VCS), synthesized in Design Compiler (DC), and backend design (Layout) in Innovus and Virtuoso using SCL 180 nm Standard cell library. The average powers of 320 μW and 932 μW are achieved through post-synthesis, excluding IO pads, and post Layout simulation, including IO pads.