Area Efficient and Low Power Half Subtractor Using Transmission Gate CMOS Logic

With the growing requirement of mobile and power saving devices, area efficient, low power and high speed applications are of paramount at present. Miniaturization of a system can be achieved by reducing the size of its basic building blocks. To address these issues, this paper includes proposals for two half subtractor de-signs which are compared to the existing 14 transistor half subtractor design as reported in the literature. The proposed half subtractors are designed using 12 transistors and 11 transistors, respectively. These half subtractors are simulated at various supply voltages, i.e., 0.6V, 0.8V, 0.9V and 1V and in different technologies, which are 45nm, 32nm and 16nm technologies respectively. The comparative analysis of the simulation results expresses that the proposed designs are much better in terms of power consumption, area efficiency and performance.