A 0.5-4GHz Full-Duplex Receiver with Multi-Domain Self-Interference Cancellation Using Capacitor Stacking Based Second-Order Delay Cells in RF Canceller

Nanosecond-scale on-chip delay is critical for integrated wideband self-interference cancellation (SIC) in full-duplex (FD) system, especially for radio frequency (RF) domain SIC. In this paper, we presented a FD receiver with multi-domain SIC using capacitor stacking based second-order delay cell in the RF canceller which breaks the trade-off between delay, loss, size and noise. A prototype is fabricated in 65nm CMOS process. The FD receiver can operate in 0.5-4GHz with gain of 29-32dB. At 2GHz local oscillator (LO) frequency, the RF canceller can achieve delay of 2-8ns while consuming 10mW. The baseband (BB) canceller can achieve delay of 9-15ns while consuming 4.4mW. These large nanosecond-scale delays ensure more than 34dB SIC over 20MHz modulated signal bandwidth in case of applying a commercial circulator (isolation of 23-26dB). In FD mode, the RF and BB cancellers degrade the receiver noise figure (NF) by 0.9dB and 0.4dB, respectively. The receiver power handling is improved by 11.5dB. The active chip area is only 0.4mm².

I. Introduction

Motivated by the ability of full-duplex (FD) wireless system to alleviate the lack of spectrum resources, wideband self-interference cancellation (SIC) techniques have recently received great attention to solve the main bottleneck in the practical application of FD system [1]–[6]. Fig. 1 shows a typical FD system structure, the actual signal delay from transmitter (TX) to receiver (RX) is as high as~ 10ns [4]. Therefore, nanosecond-scale on-chip group delay is crucial to reconstruct the self-interference (SI) signal for better SIC, esp. for RF domain SIC, since better RF domain SIC can release the RX linearity and increase the RX power handling to SI signal. Transmission lines and passive LC-based delay cells are unacceptable for integrated SIC due to bulky size.