Reduced March SR Algorithm for Deep-Submicron SRAM Testing

Memory Built-In Self-Test (BIST) is a common method to test embedded memories on a chip owing to its fast and low-cost testing. Its efficiency depends on the complexity and the fault coverage offered by its implemented test algorithm. Test algorithms with higher complexities result in longer test times and higher costs. Hence, many research works were proposed to reduce the complexity of the existing algorithm while preserving its fault coverage. This paper presents a method to reduce the March SR algorithm complexity (14N) by analyzing and removing redundant test operations from its test sequence. It was targeted for fault detection in deep-submicron SRAM. The newly produced March mSR algorithm, with 1N complexity lesser than the March SR algorithm but offers the same coverage of the intended faults, was implemented in a Memory BIST controller. The simulations successfully validated its test time reduction, functionality, and fault coverage.