Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture

Sub-sampling radios are not considered as mixer-first receivers due to high-IF down-conversion and difficulty in providing the impedance matching at the RF port. These issues are addressed in this work by proposing a scheme for direct down-conversion sub-sampling RF front-end and also a scheme for impedance matching at the RF port by using subsampling frequency(f
s
) harmonics and an eight-path mixer. In the proposed scheme, the third harmonic of the f
s
is used for direct down-conversion to zero-IF. Hence, the proposed sub-sampling receiver architecture outperforms RF sampling receivers in terms of clock generation circuit power, thanks to the low operating clock frequency of the sub-sampling RF radio. The architecture is simulated and the performance is verified using technology scalable components like switches, capacitors, and inverters for the standard IEEE 802.15.4. It is observed that the proposed digitally intensive architecture performance predicted by analytical equations is in agreement with post-layout Spectre RF simulations. The mixer-first architecture achieves a noise Figure of 8.6 dB, conversion gain of 21 dB, IIP
3
of −1 dBm, and the input impedance is matched to 50 $\Omega$ antenna impedance.