Research on VT Window Improvement Process of 55Nm SONOS Eflash Cell

In this work, two kinds of Vt window improvement directions are confirmed. For one thing, the overall improvement of Vt is confirmed which widens the difference between Vtp and Vtpi. For another, the uniformity of Vt is improved which makes the Vt distribution of all bits in the Cell more convergent. Based on the double liner process, STI corner rounding is adjusted according to STI step height and ONO film profile is optimized so that the effective area of ONO film on AA is greatly expanded. Secondly, well merge scheme is adopted. The well implant of 2T structure in Cell area is performed together and the Vt implant is performed separately, which significantly improves the uniformity of well implant in the whole cell area. At the same time, the thickness of photoresist applied on 2T structure in Vt IMP process is thinned experimentally, which is expected to effectively improve the CD uniformity within wafer and the process stability. After the above process optimization conditions are online, WAT parameters related to cell can be significantly improved, of which Vtp is increased by 15% and standard deviation is decreased by 37%.