Abstract:
The transparency of latches leads to complicated timing analysis because it allows critical long and short paths to be extended across multiple combinational stages. In t...Show MoreMetadata
Abstract:
The transparency of latches leads to complicated timing analysis because it allows critical long and short paths to be extended across multiple combinational stages. In this paper, we propose an algorithm to perform the timing analysis of latch-based circuit by modeling it as a minimum cost-to-time ratio problem. Traditionally, timing analysis of latch-based circuit usually uses linear programming (LP) or iterative methods, which may take huge runtime. By using this approach, we can greatly reduce the runtime and optimize the timing performance through the time borrowing on the critical path. Experimental results on the FPGA's VPR benchmarks by reconfiguring flip-flops as latches show that the runtime can be reduced by 136.69% on average with the same critical paths found by LP. Furthermore, our latch-based optimization provides 10.02% performance improvement on average over the original flip-flop-based designs, without changing the placement and routing results.
Date of Conference: 20-21 June 2022
Date Added to IEEE Xplore: 23 August 2022
ISBN Information: