Self-Timed Storage Register Cases

Self-timed circuits have a number of advantages over synchronous counterparts. They are hazard-free under any conditions, and delay insensitive (their behavior does not depend on the cell’s delays). They also detect any permanent fault. However, two-phase discipline (working state and spacer one) and obligatory indication subcircuit lead to some redundancy in ST circuit hardware. Practical ST circuit characteristics depend on the effectiveness of architectural, algorithmic and circuit solutions used during their design. This paper proposes and analyzes circuit solutions for the ST register implementations storing intermediate data. It discusses the implementation peculiarities of the ST storage register variants used in the ST pipeline and gives recommendations on their application. The paper proves that ST storage registers on Muller’s C-elements have the best parameters compared with the register’s implementations on RS-latch and RS-flip-flop. It is 1.5 – 2.1 times simpler than other possible implementations. Besides, it is invariant to the input spacer type up to the indication cell type.