Gate-Termination Frequency Adaptation in a Self-Synchronous Inverse Class-F Rectifier

Owing to the time-reversal duality principle, the circuit of a power amplifier (PA) can be used as a rectifier. Such a rectifier is called a self-synchronous rectifier. In this case, the drain-side network of a PA is fed by the RF-power and the drain bias, connected to a DC-load, obtains rectified dc voltage. When the drain-side network is properly laid out for PA operation, the same network is appropriate for rectifier operation. The gate-side network is crucial for proper rectification, as it provides the synchronous excitation to the transistor gate. Its ideal configuration, however, differs from that of the PA mode. In this paper, the effects of changing the gate-side parameters termination resistance and bias voltage on a class-F^-1 self-synchronous rectifier are reported. We present, to the authors’ best knowledge, for the first time a shift in the frequency at which maximum rectification efficiency is achieved from 2.28 GHz to 2.44 GHz by a change in the gate termination resistance from 0 Ω to an open circuit, while the frequency steadily increases with increasing resistance. Consequently, peak efficiency of the rectifier can be shifted and controlled.

I. Introduction

At low AC frequencies, like wireless charging applications, diode rectifiers can accomplish high-efficiency RF-to-DC rectification even at high power [1]. When the frequency increases to several gigahertz, the power handling capability of diode rectifiers is very limited, as either the breakdown voltage of the diode is too low, its parasitic elements too large, or its recovery time too long. To accomplish efficient rectification of gigahertz-frequency RF signals at high input power, rectifiers using transistors have gained interest in recent years [2], [3]. One way to establish rectification with a transistor device is by making use of the time-reversal duality principle [4]. This principle states that a power amplifier can be operated as a rectifier without changing any of the drain-side circuitry [5]. In power amplifier configuration, an RF input power is fed through a gate-side network to the gate of a transistor with a gate bias of V_G, as shown in Fig. 1a. The drain of the transistor is biased at a voltage V_D, which provides the dc input power, and the amplified RF output power is delivered to the load through the drain-side network. To operate the same circuit as a rectifier, as shown in Fig. 1b, the drain-side network is fed by the RF input power, and the gate is still biased at a voltage V_G, while the gate side network is terminated by a resistance R_G. The rectified dc output power is delivered to the drain bias point where the load resistance, R_L, is connected. The circuit depicted in Fig. 1b relies on the parasitic capacitance between the gate and the drain terminal of the transistor to couple some of the input power to the gate side. The operation mode is therefore called self-synchronous. A distinction is made between a self-synchronous and a synchronous rectifier [6]. In the synchronous rectifier power is purposefully fed to the gate via a coupler and a phase shifter, as shown in Fig. 1c. The successful realisation of self-synchronous rectifiers has been reported in numerous papers for several power amplifier classes, from linear amplifiers, like class-C [7], to switch-mode amplifiers, like class-E [8], F [9] or F^-1 [10]. As switch-mode designs usually can only deliver rectification at a narrow frequency band [7], the research on increasing the bandwidth for these devices is ongoing. Fig. 1:

Simplified diagrams of a transistor circuit operating as a power amplifier (a), as a self-synchronous rectifier (b) and a synchronous rectifier (c).

Fig. 2:

Photograph of the self-synchronous rectifier. The board size is 69 × 55.3 mm².