Performance of n- and p-ch self-aligned planar double-gate Cu-MIC poly-Ge TFTs on glass substrates

A three-dimensional (3D) stack of transistors is an attractive method for achieving high-density integration. The upper transistor must be fabricated at a low temperature to avoid adversely affecting the lower transistor. Germanium (Ge) has a lower melting point and higher mobility compared to silicon (Si). Thus, they are ideal transistors for the upper layer of a 3D-LSI. In this experiment, crystallization was realized using copper (Cu) metal-induced crystallization, and high performance was achieved using a self-aligned planar double-gate structure. The transfer and output characteristics showed that the on-current of the n-ch TFT was one order of magnitude lower than that of the p-ch TFT. This may be caused by the Schottky barrier formation at the n-type poly-Ge/metal SD interface.