High-Level Methods for Hardware IP Protections: Solutions, Trends, and Challenges

Due to the globalization of the semiconductor supply chain, the security threats for the production of an integrated circuit (IC) and its intellectual property (IP) are becoming more and more critical for many fab-less design houses. Conversely, the protections for these threats are expensive, especially when introduced in the last stages of the design flow. In this paper, we discuss the approaches, the trends, and the associated challenges that can be applied in the early stages of the design, i.e., before logic synthesis. On one hand, these approaches can operate on more semantic information and offer more protection. On the other hand, they have more effects on the overall design and need to somehow “predict” the effects on the final implementation.