Probability-Based DSE of Approximated LUT-Based FPGA Designs

We present a novel simulation-free Design Space Exploration (DSE)-based methodology for approximating Look-Up Table (LUT)-based Field-Programmable Gate Array (FPGA) designs. This approach aims to reduce the number of LUTs without increasing the length of the Critical Path (CP). It incorporates a fast error estimation technique for modeling the error observable at the Primary Outputs (POs) through the propagation of signal switching probabilities between LUTs. Key to the approach is the elimination of cones according to their output Truth Densities (TDs). For multi-objective optimization, the algorithm NSGA-II was adopted for steering the DSE. With as many genes as LUTs within a given LUT design, each probability-based real-valued genotype corresponds to a new approximation candidate. The presented methodology was implemented within the synthesis tool ABC. It showcased Pareto-efficient solutions with a 47 % lower volume of the dominated portion of the objective space w.r.t the state of the art.