I. Introduction
Reconfigurable computing has contributed to the eminent progression in a wide scope of utilizations – from high performance computing to secure systems. Despite the fact that LUT-based FPGAs have been the most popular reconfigurable computing platform, there are a few other alternative reconfigurable platforms based on fine-granularity programmability [1], [2]. Specifically, the TRAnsistor-level Programmable fabric (TRAP) [3], has received interest recently as it illustrates uniquely compelling features, such as: (1) A more compact embedded field-programmable gate array (eFPGA) for hardware obfuscation [4], in which a small but crucial part of the design is implemented on an on-chip eFPGA and the rest is implemented by a conventional application-specific integrated circuit (ASIC); (2) A better logic density and lower area overhead compared to conventional eFPGAs for the same technology. However, accurate timing analysis of transistor-level programmable fabrics has been a challenge.